Thermal Interface Material (TIM) serves as the critical intermediate layer connecting chips and heat sinks. Micro‑scale surface irregularities exist on chips, package lids and heat sinks. After assembly, residual air gaps hinder outward heat dissipation. TIM fills these gaps and enables efficient heat transfer from chips to heat sinks or liquid cold plates.

Chip packages fall into two architectures: lidded and lid‑less, depending on whether a metal package lid is implemented.

For lidded packages, heat transfers following the path: Chip → TIM1 → Package Lid → TIM2 → Heat Sink. The lid delivers mechanical protection, electrical isolation and heat‑spreading functions for the chip. For lid‑less packages, the lid is eliminated. Heat flows via Chip → TIM1.5 → Heat Sink. Heat sinks / cold plates attach directly to bare dies. This creates shorter thermal paths with fewer material interfaces for superior cooling efficiency. However, chips lose lid‑provided isolation and protection, imposing stricter requirements on interface material conformability and assembly‑force control. As power consumption and heat‑flux density keep rising for AI and high‑performance‑computing chips, lid‑less architectures gain wider adoption for their shortened thermal conduction paths.

TIM performance requirements for different positions differ in thermal conductivity, electrical insulation and compliance:

1. TIM1: Located between bare die and package lid. It forms the primary thermal‑export interface for chips. Exposed directly to hot chips, TIM1 endures peak operating temperatures and heat‑flux densities with the most stringent requirements for thermal performance and interfacial reliability (higher cooling demand than TIM2). Common options include metal‑based materials such as indium foils, solders and liquid metals; or polymer‑based materials like thermal adhesives, thermal greases and phase‑change materials.

2. TIM2: Sits between package lid and heat sink, transferring heat to external cooling systems. Further away from heat sources and operating at lower temperatures than TIM1, TIM2 mainly fills gaps and accommodates assembly tolerances. Good compression‑recovery and conformability are prioritized while insulation requirements are moderate. Typical products: thermal grease, thermal pads and phase‑change materials.

3. TIM1.5: Applied between bare die and heat sink within lid‑less packages. It yields shorter thermal paths and lower thermal resistance, yet chips bear direct assembly pressure. Materials must offer effective heat dissipation plus compliant resilience to absorb chip warpage and prevent die damage. Representative solutions are high‑performance phase‑change materials, liquid metals and oriented‑graphene thermal pads.

TIM generally consists of a polymer matrix and thermally conductive fillers, whose combined properties define thermal and mechanical performance. Matrices deliver flowability, compliance and mechanical stability (silicone oil, silicone rubber, resin, etc.). Fillers boost thermal conductivity, including ceramic fillers (alumina, boron nitride) and carbon‑based fillers (graphene, carbon fiber).

Take phase‑change TIM as an example: paraffin or polyolefin act as phase‑change matrices. High‑conductivity fillers are incorporated to build oriented thermal‑conduction networks and improve internal heat transport. Flexible carriers, solid‑state phase‑change structures or micro‑encapsulation restrain material flow during phase transition and enhance dimensional stability, balancing thermal conductivity, interfacial conformability and long‑term reliability.

TIM technologies are grouped into three major categories: polymer‑based, metal‑based and carbon‑based:

1. Polymer‑based TIM: Silicone‑dominated systems. Silicone oil / silicone‑rubber matrices loaded with ceramic, metallic or carbon conductive particles produce thermal grease, gels and silicone pads. Merits include high compliance, easy processing and good interface adaptability. Main product forms: thermal grease, thermal gels, thermal pads and phase‑change thermal materials.

2. Metal‑based TIM: Low‑melting‑point metals and alloys function as primary heat‑transfer media. Main examples: liquid metal, indium foils and low‑temperature solders. High intrinsic thermal conductivity plus interfacial wetting properties reduce thermal resistance; performance can be further enhanced via composite high‑conductivity additives.

3. Carbon‑based TIM: Graphene, carbon fiber or carbon nanotubes serve as thermal conductors or skeleton structures compounded with silicone/resin matrices. Orientation design and continuous thermal networks are deployed to enhance through‑thickness heat transfer. Typical products: oriented‑graphene thermal pads and carbon‑fiber thermal pads.

Common thermal‑interface products: thermal pads, thermal grease, thermal gels, phase‑change thermal materials, liquid‑metal materials, graphene thermal pads and soldering materials.

Rising chip power and advanced‑package evolution drive TIM toward higher thermal conductivity and reliability

Power draw of AI servers keeps climbing, with single‑GPU power ramping toward the kilowatt level, spurring demand for high‑performance TIM. For NVIDIA platforms, total system power of DGX A100, DGX B200 and the new‑generation DGX Rubin NVL8 reaches 6.5 kW, 14.3 kW and ~24 kW respectively; Rubin’s power is approximately 3.7 × that of A100. Meanwhile single‑GPU power rises from 400 W (A100) to 1000 W (HGX B200), and peaks at 1400 W for GB300 GPUs (3.5 × A100). Higher heat output per chip pushes up requirements for chip‑to‑heat‑sink interfacial heat transfer, calling for TIM upgrades with higher thermal conductivity, lower thermal resistance and enhanced reliability.

Growing chip heat‑flux density makes temperature control critical for chip performance and reliability. As GPU power increases, heat output per unit die area rises and local hot‑spot cooling becomes more challenging. Junction temperature directly governs long‑term device reliability: elevated junction temperature sharply accelerates failure rates and shortens component service life.

Advanced packaging evolves toward higher integration and 2.5D/3D architectures, further raising cooling and TIM requirements. AI‑chip advancement drives packaging migration from traditional wire‑bonding and flip‑chip to wafer‑level packaging and 2.5D/3D advanced packaging. Dice are densely integrated with HBM and other devices through interposers and advanced interconnects, boosting I/O counts and interconnect density. Higher integration packs more high‑power devices within each package area.

 Co‑integration of dice, silicon interposers and substrates adds complexity to thermal‑path management.

Larger package dimensions and heterogeneous‑material integration exacerbate package warpage. Coefficients‑of‑thermal‑expansion mismatch generates thermo‑mechanical stress during reflow and thermal cycling. Larger packages amplify height offset and local deformation between die, substrate and heat sink, creating uneven TIM thickness and contact pressure that produce localized high‑thermal‑resistance zones. Consequently, TIM specifications for advanced packages evolve from simple high‑conductivity targets to combined requirements for high thermal conductivity, low thermal resistance, low mechanical stress and high resilience.

High power consumption together with large‑format advanced packages escalate TIM performance demands and expose trade‑offs within conventional polymer TIM. Polymer‑based TIM improves thermal performance by loading conductive fillers into grease/gel/phase‑change matrices yet remains limited by the low thermal conductivity of polymer hosts. Most commercial thermal greases, gels and pads deliver single‑digit W/(m·K) thermal conductivity; state‑of‑the‑art high‑performance phase‑change materials achieve around 8.5 W/(m·K). Higher filler loading boosts thermal conductivity but increases viscosity and stiffness, degrading wetting, gap‑filling and compliance.

For kilowatt‑class AI chips housed in large‑format advanced packages, TIM must simultaneously dissipate intense heat and accommodate large interfacial height variations and mechanical deformation, making the performance balance for traditional polymer TIM increasingly difficult.

Metal‑based TIM delivers superior thermal conductivity yet faces greater interfacial‑compatibility and reliability challenges for large‑area advanced packages. Indium and liquid‑metal TIM offer thermal conductivity ranging 20‑80 W/(m·K) to reduce bulk‑material thermal resistance. Practical deployment must address oxidation risk, corrosion risk, electrical conductivity, leakage hazard and assembly complexity. Large warpage and uneven contact pressure across oversized packages impose stricter demands on material ductility and interfacial conformability. Additionally flowable TIM like thermal grease may suffer from pump‑out, oil bleeding and dry‑out over long‑term thermal cycling, deteriorating interfaces and raising thermal resistance.

Hence high‑end AI chips require TIM solutions that satisfy a combined set of specifications: high thermal conductivity, low thermal resistance, low stress, high resilience and long‑term operational reliability.

Xianyi Electronics Indium‑Foil TIM

Xianyi’s indium‑foil TIM is a flexible thermal‑interface material precision‑fabricated from high‑purity indium metal. Leveraging indium’s unique material properties, it fits high‑temperature, high‑power applications requiring stringent long‑term reliability.

Key Features

• Thermal conductivity up to 86 W/(m·K)

• Excellent plasticity and ductility

• Dimensional tolerance: ±0.03 mm (length & width); thickness tolerance ±0.01 mm

Indium Foils for TIM1 Application

• Void fraction <2 % when paired with Xianyi proprietary flux

• Low‑oxygen composition, compatible with flux‑free soldering

• Pre‑flux‑coatable option to simplify packaging workflows

Indium Foils for TIM1.5 & TIM2 Application

• Customizable surface textures for substantial contact‑thermal‑resistance reduction

• Barrier‑layer plating available to prevent adhesion and contamination

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